There is no reason for the delay, in each loop iteration, while polling for
link up (PCIE_LINK_WAIT_SLEEP_MS), to be so long as 90 ms.
PCIe r6.0, sec 6.6.1, still require us to wait for up to 1.0 s for the link
to come up, thus the number of retries (PCIE_LINK_WAIT_MAX_RETRIES) is
increased to keep the total timeout to 1.0 s.
PCIe r6.0, sec 6.6.1, also mandates that there is a 100 ms delay, after the
link has been established, before performing configuration requests (this
delay already exists in dw_pcie_wait_for_link() and is unchanged).
Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@xxxxxxx>
Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-designware.c | 6 +++++-
drivers/pci/pci.h | 11 ++++++++---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928..d7278f6b84c1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -701,7 +701,11 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
u32 offset, val;
int retries;
- /* Check if the link is up or not */
+ /*
+ * Check if the link is up or not. As per PCIe r6.0, sec 6.6.1, software
+ * must allow at least 1.0 s following exit from a Conventional Reset of
+ * a device, before determining that the device is broken.
+ */
for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (dw_pcie_link_up(pci))
break;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 43cb77c27ac0..9d20f0222fb1 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -56,9 +56,14 @@ struct pcie_tlp_log;
*/
#define PCIE_RESET_CONFIG_WAIT_MS 100
-/* Parameters for the waiting for link up routine */
-#define PCIE_LINK_WAIT_MAX_RETRIES 10
-#define PCIE_LINK_WAIT_SLEEP_MS 90
+/*
+ * Parameters for waiting for a link to be established. As per PCIe r6.0,
+ * sec 6.6.1, software must allow at least 1.0 s following exit from a
+ * Conventional Reset of a device, before determining that the device is broken.
+ * Therefore LINK_WAIT_MAX_RETRIES * LINK_WAIT_SLEEP_MS should equal 1.0 s.
+ */
+#define PCIE_LINK_WAIT_MAX_RETRIES 100
+#define PCIE_LINK_WAIT_SLEEP_MS 10
/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
#define PCIE_MSG_TYPE_R_RC 0
--
2.49.0
