On Fri, Jun 13, 2025 at 02:21:59AM -0300, Geraldo Nascimento wrote: > Current code may fail Gen2 retraining if Target Link Speed > is set to 2.5 GT/s in Link Control and Status Register 2. > Set it to 5.0 GT/s accordingly. > > Signed-off-by: Geraldo Nascimento <geraldogabriel@xxxxxxxxx> > --- > drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > index 65653218b9ab..68634ae8caaf 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > * Enable retrain for gen2. This should be configured only after > * gen1 finished. > */ > + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > + status |= FIELD_PREP(PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_5_0GT); Although this incidentally "works" for facilitating Gen2 training because mask clears 2.5 GT/s, this will shift the value 0x2 by the mask I think. This is clearly wrong, and instead we should use AND clearing plus OR'ing the 5.0GT/s value. But I wait until at least Bjorn's review to send v4 with correction. Geraldo Nascimento
