During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE. --- V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion V1 -> V2: use standard PCIe defines as suggested by Bjorn Geraldo Nascimento (5): PCI: rockchip-host: Use standard PCIe defines PCI: rockchip: Drop unused custom registers and bitfields PCI: rockchip-host: Set Target Link Speed before retraining phy: rockchip-pcie: Enable all four lanes phy: rockchip-pcie: Adjust read mask and write drivers/pci/controller/pcie-rockchip-host.c | 48 +++++++++++---------- drivers/pci/controller/pcie-rockchip.h | 11 +---- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 ++++--- 3 files changed, 36 insertions(+), 39 deletions(-) -- 2.49.0
