Re: [PATCH] wifi: ath11k: pci: Fix msi_irq crash on driver unload with QCN9074 PCIe WiFi 6 modules

[Balsam Chihi <balsam.chihi@xxxxxxxxxxx>]

I had to skip all "ath11k_pcic_read32()" calls to avoid the kernel crash.
When booting and loading the driver the  "ath11k_pcic_read32()" does
not cause any issues, only when unloading, rebooting and poweroff the
problem appears.
I will send the boot and reboot logs as soon as possible (probably
monday, when i get my hands on the target device).
and this is the diff that worked for me, that replaces the initial patch :

--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -201,16 +201,18 @@ static void ath11k_pci_soc_global_reset(
  ath11k_warn(ab, "link down error during global reset\n");
 }

-static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
+static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab,
bool power_on)
 {
- u32 val;
+ if (power_on) {
+ u32 val;

- /* read cookie */
- val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
+ /* read cookie */
+ val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);

- val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
+ val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
+ }

  /* TODO: exact time to sleep is uncertain */
  mdelay(10);
@@ -221,14 +223,18 @@ static void ath11k_pci_clear_dbg_registe
  ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
  mdelay(10);

- val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
+ if (power_on) {
+ u32 val;

- /* A read clear register. clear the register to prevent
- * Q6 from entering wrong code path.
- */
- val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
+ val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
+
+ /* A read clear register. clear the register to prevent
+ * Q6 from entering wrong code path.
+ */
+ val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
+ }
 }

 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
@@ -366,7 +372,7 @@ static void ath11k_pci_sw_reset(struct a
  }

  ath11k_mhi_clear_vector(ab);
- ath11k_pci_clear_dbg_registers(ab);
+ ath11k_pci_clear_dbg_registers(ab, power_on);
  ath11k_pci_soc_global_reset(ab);
  ath11k_mhi_set_mhictrl_reset(ab);
 }