As IP cores are aligned by 0x10000, increase the size of all system
register instances to the maximum (0x10000) to allow using accessing
registers over the currently set limit.
Suggested-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
---
Did not add the r-b from Sam, as the patch is pretty much completely
reworked, including the description. Please send it again :).
---
arch/arm64/boot/dts/exynos/exynos2200.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
index 943e83851..b3a8933a4 100644
--- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
@@ -306,7 +306,7 @@ cmu_peric0: clock-controller@10400000 {
syscon_peric0: syscon@10420000 {
compatible = "samsung,exynos2200-peric0-sysreg", "syscon";
- reg = <0x10420000 0x2000>;
+ reg = <0x10420000 0x10000>;
};
pinctrl_peric0: pinctrl@10430000 {
@@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 {
syscon_peric1: syscon@10720000 {
compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
- reg = <0x10720000 0x2000>;
+ reg = <0x10720000 0x10000>;
};
pinctrl_peric1: pinctrl@10730000 {
@@ -418,7 +418,7 @@ cmu_ufs: clock-controller@11000000 {
syscon_ufs: syscon@11020000 {
compatible = "samsung,exynos2200-ufs-sysreg", "syscon";
- reg = <0x11020000 0x2000>;
+ reg = <0x11020000 0x10000>;
};
pinctrl_ufs: pinctrl@11040000 {
@@ -450,7 +450,7 @@ cmu_peric2: clock-controller@11c00000 {
syscon_peric2: syscon@11c20000 {
compatible = "samsung,exynos2200-peric2-sysreg", "syscon";
- reg = <0x11c20000 0x4000>;
+ reg = <0x11c20000 0x10000>;
};
pinctrl_peric2: pinctrl@11c30000 {
@@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 {
syscon_cmgp: syscon@14e20000 {
compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
- reg = <0x14e20000 0x2000>;
+ reg = <0x14e20000 0x10000>;
};
pinctrl_cmgp: pinctrl@14e30000 {
--
2.43.0
