Hi,
Two small fixes for Exynos990 CMU_TOP:
Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and
CMUREF mux/div, and update clock IDs.
Fix mux/div bit widths and replace a few bogus divs with fixed-factor
clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate.
Please review.
Denzeel Oliva
Signed-off-by: Denzeel Oliva <wachiturroxd150@xxxxxxxxx>
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Denzeel Oliva (3):
clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
dt-bindings: clock: exynos990: Reorder IDs clocks and extend
clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
drivers/clk/samsung/clk-exynos990.c | 154 +++++++++++++++----------
include/dt-bindings/clock/samsung,exynos990.h | 402 ++++++++++++++++++++++++++++++++--------------------------------
2 files changed, 297 insertions(+), 259 deletions(-)
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base-commit: 886e5e7b0432360842303d587bb4a65d10741ae8
change-id: 20250819-2-ab6c8bdf07d7
Best regards,
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Denzeel Oliva <wachiturroxd150@xxxxxxxxx>
