Hi Denzeel,
Thanks for your patches.
On Wed Aug 20, 2025 at 12:19 AM CEST, Denzeel Oliva wrote:
> Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL,
> HSI0/1/2). Replace wrong divs with fixed-factor clocks for
> HSI1/2 PCIe and USBDP debug. Also fix OTP rate. These align
> with Exynos990 downstream cmucal and ensure correct parent/rate
> selection.
>
[snip]
> @@ -837,7 +837,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
> CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
> - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 1),
> DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
> CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
As per the downstream clock driver, PLL_SHARED0_DIV3 has a divratio of
0, 2. Was there any reason to change this? [1]
[1] https://github.com/pascua28/android_kernel_samsung_s20fe/blob/3be539e9cd22b89ba3cc8282945a0c46ff27341d/drivers/soc/samsung/cal-if/exynos9830/cmucal-sfr.c#L3935
Best regards,
Igor
