On 18-08-25, 13:11, Pritam Manohar Sutar wrote:
> > > + /* check cr_para_ack*/
> > > + cnt = 0;
> > > + do {
> > > + /*
> > > + * data symbols are captured by phy on rising edge of the
> > > + * tx_clk when tx data enabled.
> > > + * completion of the write cycle is acknowledged by
> assertion
> > > + * of the cr_para_ack.
> > > + */
> > > + exynosautov920_usb31drd_cr_clk(phy_drd, true);
> > > + reg = readl(reg_phy +
> > EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> > > + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
> > > + break;
> > > +
> > > + exynosautov920_usb31drd_cr_clk(phy_drd, false);
> > > +
> > > + /*
> > > + * wait for minimum of 10 cr_para_clk cycles after phy reset
> > > + * is negated, before accessing control regs to allow for
> > > + * internal resets.
> > > + */
> > > + cnt++;
> > > + } while (cnt < 10);
> > > +
> > > + if (cnt == 10)
> > > + dev_dbg(dev, "CR write failed to 0x%04x\n", addr);
> >
> > Not error?
>
> This is only for debugging purpose. It is not considered as error.
Write failed is not an error? If this code is only for debug, pls drop
it.
--
~Vinod
