FSD SoC WDT has few changes when compared to exynos7 interms of Clocks,
PMU register bits for each cluster. So use "tesla,fsd-wdt"
compatibility for using correct driver data.
FSD supports 2 Clocks for WDT (PCLK and CLK).
- use fin_pll source Clock for all timer related calculations.
- use bus Clock (IMEM_WDT0_IPCLKPORT_PCLK) to gate/ungate the register
interface. Update both as per WDT UM.
Signed-off-by: Varada Pavani <v.pavani@xxxxxxxxxxx>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 690b4ed9c29b..ff031a630f10 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -624,30 +624,36 @@ pmu_system_controller: system-controller@11400000 {
};
watchdog_0: watchdog@100a0000 {
- compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt";
reg = <0x0 0x100a0000 0x0 0x100>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
- clocks = <&fin_pll>;
- clock-names = "watchdog";
+ clocks = <&clock_imem IMEM_WDT0_IPCLKPORT_PCLK>,
+ <&fin_pll>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,cluster-index = <0>;
};
watchdog_1: watchdog@100b0000 {
- compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt";
reg = <0x0 0x100b0000 0x0 0x100>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
- clocks = <&fin_pll>;
- clock-names = "watchdog";
+ clocks = <&clock_imem IMEM_WDT1_IPCLKPORT_PCLK>,
+ <&fin_pll>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,cluster-index = <1>;
};
watchdog_2: watchdog@100c0000 {
- compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt";
reg = <0x0 0x100c0000 0x0 0x100>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
- clocks = <&fin_pll>;
- clock-names = "watchdog";
+ clocks = <&clock_imem IMEM_WDT2_IPCLKPORT_PCLK>,
+ <&fin_pll>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,cluster-index = <2>;
};
pwm_0: pwm@14100000 {
--
2.49.0
