On 25/08/2025 07:51, Denzeel Oliva wrote: > Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL, > HSI0/1/2). Replace wrong divs with fixed-factor clocks for Separate commits. > HSI1/2 PCIe and USBDP debug. Also add OTP rate in ffactor. > These align with Exynos990 downstream cmucal and ensure correct > parent/rate selection. Fixes tags. Best regards, Krzysztof
