Hi,
Two small fixes for Exynos990 CMU_TOP:
Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and
CMUREF mux/div, and update clock IDs.
Fix mux/div bit widths and replace a few bogus divs with fixed-factor
clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate.
Changes in v2:
- In the first commit the divratio of
PLL_SHARED0_DIV3 should not be changed.
Changes in v3:
- There is no ABI massive break, the new ID clocks are
in the last define CMU_TOP block.
Changes in v4:
- Fix compilation for define CLK_DOUT_CMU_CMUREF to
CLK_DOUT_CMU_CLK_CMUREF
Please review.
Denzeel Oliva
Signed-off-by: Denzeel Oliva <wachiturroxd150@xxxxxxxxx>
---
Denzeel Oliva (4):
clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks
clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
drivers/clk/samsung/clk-exynos990.c | 136 ++++++++++++++++----------
include/dt-bindings/clock/samsung,exynos990.h | 4 +
2 files changed, 89 insertions(+), 51 deletions(-)
---
base-commit: 0f4c93f7eb861acab537dbe94441817a270537bf
change-id: 20250825-cmu-top-5c709c1d07c2
Best regards,
--
Denzeel Oliva <wachiturroxd150@xxxxxxxxx>
