The Exynos TMU driver's IRQ clear logic has been refactored for improved
maintainability and reduced code duplication. A unified
exynos4210_tmu_clear_irqs() implementation now replaces the previous
reliance on SoC-specific functions and hardcoded register mappings.
This new implementation leverages SoC-specific configuration fields
(tmu_intstat, tmu_intclear, and IRQ bit mappings) stored within
exynos_tmu_data. These fields are populated during device setup within
exynos_map_dt_data(), thereby streamlining new SoC integration, ensuring
correct interrupt handling, and improving code clarity. This refactor
simplifies the addition of new SoC support, ensures correct interrupt
handling across platforms, and improves overall code clarity.
Cc: Mateusz Majewski <m.majewski2@xxxxxxxxxxx>
Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
---
v7: new patch in this series
split the IRQ function handler per SoC.
---
drivers/thermal/samsung/exynos_tmu.c | 150 +++++++++++++++++----------
1 file changed, 96 insertions(+), 54 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 5e581055e3f3..9f94c58e1e74 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -158,6 +158,8 @@ enum soc_type {
* 0 < reference_voltage <= 31
* @tzd: pointer to thermal_zone_device structure
* @enabled: current status of TMU device
+ * @tmu_intstat: interrupt status register
+ * @tmu_intclear: interrupt clear register
* @tmu_set_low_temp: SoC specific method to set trip (falling threshold)
* @tmu_set_high_temp: SoC specific method to set trip (rising threshold)
* @tmu_set_crit_temp: SoC specific method to set critical temperature
@@ -184,6 +186,8 @@ struct exynos_tmu_data {
u8 reference_voltage;
struct thermal_zone_device *tzd;
bool enabled;
+ u32 tmu_intstat;
+ u32 tmu_intclear;
void (*tmu_set_low_temp)(struct exynos_tmu_data *data, u8 temp);
void (*tmu_set_high_temp)(struct exynos_tmu_data *data, u8 temp);
@@ -770,67 +774,90 @@ static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id)
}
static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
+{
+ unsigned int val_irq;
+ u32 tmu_intstat = data->tmu_intstat;
+ u32 tmu_intclear = data->tmu_intclear;
+
+ val_irq = readl(data->base + tmu_intstat);
+
+ /* Exynos4210 doesn't support FALL interrupts */
+ writel(val_irq, data->base + tmu_intclear);
+}
+
+static void exynos4412_tmu_clear_irqs(struct exynos_tmu_data *data)
{
unsigned int val_irq, clear_irq = 0;
- u32 tmu_intstat, tmu_intclear;
+ u32 tmu_intstat = data->tmu_intstat;
+ u32 tmu_intclear = data->tmu_intclear;
struct tmu_irq_map irq_map = {0};
- if (data->soc == SOC_ARCH_EXYNOS5260) {
- tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
- tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
- } else if (data->soc == SOC_ARCH_EXYNOS7) {
- tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
- tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
- } else if (data->soc == SOC_ARCH_EXYNOS5433) {
- tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
- tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
- } else {
- tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
- tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
+ val_irq = readl(data->base + tmu_intstat);
+
+ /* Set SoC-specific interrupt bit mappings */
+ irq_map.fall[2] = BIT(20);
+ irq_map.fall[1] = BIT(16);
+ irq_map.fall[0] = BIT(12);
+ irq_map.rise[2] = BIT(8);
+ irq_map.rise[1] = BIT(4);
+ irq_map.rise[0] = BIT(0);
+
+ /* Map active INTSTAT bits to INTCLEAR */
+ for (int i = 0; i < 3; i++) {
+ if (val_irq & irq_map.fall[i])
+ clear_irq |= irq_map.fall[i];
+ if (val_irq & irq_map.rise[i])
+ clear_irq |= irq_map.rise[i];
}
+ if (clear_irq)
+ writel(clear_irq, data->base + tmu_intclear);
+}
+
+static void exynos5420_tmu_clear_irqs(struct exynos_tmu_data *data)
+{
+ unsigned int val_irq, clear_irq = 0;
+ u32 tmu_intstat = data->tmu_intstat;
+ u32 tmu_intclear = data->tmu_intclear;
+ struct tmu_irq_map irq_map = {0};
+
val_irq = readl(data->base + tmu_intstat);
- /* Exynos4210 doesn't support FALL interrupts */
- if (data->soc == SOC_ARCH_EXYNOS4210) {
- writel(val_irq, data->base + tmu_intclear);
- return;
+ /* Set SoC-specific interrupt bit mappings */
+ irq_map.fall[2] = BIT(24);
+ irq_map.fall[1] = BIT(20);
+ irq_map.fall[0] = BIT(16);
+ irq_map.rise[2] = BIT(8);
+ irq_map.rise[1] = BIT(4);
+ irq_map.rise[0] = BIT(0);
+
+ for (int i = 0; i < 3; i++) {
+ if (val_irq & irq_map.fall[i])
+ clear_irq |= irq_map.fall[i];
+ if (val_irq & irq_map.rise[i])
+ clear_irq |= irq_map.rise[i];
}
+ if (clear_irq)
+ writel(clear_irq, data->base + tmu_intclear);
+}
+
+static void exynos5433_tmu_clear_irqs(struct exynos_tmu_data *data)
+{
+ unsigned int val_irq, clear_irq = 0;
+ u32 tmu_intstat = data->tmu_intstat;
+ u32 tmu_intclear = data->tmu_intclear;
+ struct tmu_irq_map irq_map = {0};
+
+ val_irq = readl(data->base + tmu_intstat);
+
/* Set SoC-specific interrupt bit mappings */
- switch (data->soc) {
- case SOC_ARCH_EXYNOS3250:
- case SOC_ARCH_EXYNOS4412:
- case SOC_ARCH_EXYNOS5250:
- case SOC_ARCH_EXYNOS5260:
- irq_map.fall[2] = BIT(20);
- irq_map.fall[1] = BIT(16);
- irq_map.fall[0] = BIT(12);
- irq_map.rise[2] = BIT(8);
- irq_map.rise[1] = BIT(4);
- irq_map.rise[0] = BIT(0);
- break;
- case SOC_ARCH_EXYNOS5420:
- case SOC_ARCH_EXYNOS5420_TRIMINFO:
- irq_map.fall[2] = BIT(24);
- irq_map.fall[1] = BIT(20);
- irq_map.fall[0] = BIT(16);
- irq_map.rise[2] = BIT(8);
- irq_map.rise[1] = BIT(4);
- irq_map.rise[0] = BIT(0);
- break;
- case SOC_ARCH_EXYNOS5433:
- case SOC_ARCH_EXYNOS7:
- irq_map.fall[2] = BIT(23);
- irq_map.fall[1] = BIT(17);
- irq_map.fall[0] = BIT(16);
- irq_map.rise[2] = BIT(7);
- irq_map.rise[1] = BIT(1);
- irq_map.rise[0] = BIT(0);
- break;
- default:
- pr_warn("exynos-tmu: Unknown SoC type %d, using fallback IRQ mapping\n", soc);
- break;
+ irq_map.fall[2] = BIT(23);
+ irq_map.fall[1] = BIT(17);
+ irq_map.fall[0] = BIT(16);
+ irq_map.rise[2] = BIT(7);
+ irq_map.rise[1] = BIT(1);
+ irq_map.rise[0] = BIT(0);
/* Map active INTSTAT bits to INTCLEAR */
for (int i = 0; i < 3; i++) {
@@ -915,6 +942,8 @@ static int exynos_map_dt_data(struct platform_device *pdev)
data->tmu_control = exynos4210_tmu_control;
data->tmu_read = exynos4210_tmu_read;
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
+ data->tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
+ data->tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
data->gain = 15;
data->reference_voltage = 7;
data->efuse_value = 55;
@@ -934,7 +963,14 @@ static int exynos_map_dt_data(struct platform_device *pdev)
data->tmu_control = exynos4210_tmu_control;
data->tmu_read = exynos4412_tmu_read;
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
- data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
+ data->tmu_clear_irqs = exynos4412_tmu_clear_irqs;
+ if (data->soc == SOC_ARCH_EXYNOS5260) {
+ data->tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
+ data->tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
+ } else {
+ data->tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
+ data->tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
+ }
data->gain = 8;
data->reference_voltage = 16;
data->efuse_value = 55;
@@ -952,7 +988,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
data->tmu_control = exynos4210_tmu_control;
data->tmu_read = exynos4412_tmu_read;
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
- data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
+ data->tmu_clear_irqs = exynos5420_tmu_clear_irqs;
+ data->tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
+ data->tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
data->gain = 8;
data->reference_voltage = 16;
data->efuse_value = 55;
@@ -969,7 +1007,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
data->tmu_control = exynos5433_tmu_control;
data->tmu_read = exynos4412_tmu_read;
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
- data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
+ data->tmu_clear_irqs = exynos5433_tmu_clear_irqs;
+ data->tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
+ data->tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
data->gain = 8;
if (res.start == EXYNOS5433_G3D_BASE)
data->reference_voltage = 23;
@@ -989,7 +1029,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
data->tmu_control = exynos7_tmu_control;
data->tmu_read = exynos7_tmu_read;
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
- data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
+ data->tmu_clear_irqs = exynos5433_tmu_clear_irqs;
+ data->tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
+ data->tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
data->gain = 9;
data->reference_voltage = 17;
data->efuse_value = 75;
--
2.50.1
