Exynos PCI file follows MACRO definition order where register offset is defined in ascending order and each bit field within the offset is defined right after offset definition. Some MACROs are out of order and so reorder those MACROs to maintain consistency. Suggested-by: Hrishikesh Dileep <hrishikesh.d@xxxxxxxxxxx> Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx> --- drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 30d12ff9b0c6..b4ec167b0583 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -27,11 +27,11 @@ /* PCIe ELBI registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_IRQ_INTA_ASSERT BIT(0) #define EXYNOS_IRQ_INTB_ASSERT BIT(2) #define EXYNOS_IRQ_INTC_ASSERT BIT(4) #define EXYNOS_IRQ_INTD_ASSERT BIT(6) -#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 #define EXYNOS_PCIE_SW_WAKE 0x018 @@ -42,9 +42,9 @@ #define EXYNOS_PCIE_NONSTICKY_RESET 0x024 #define EXYNOS_PCIE_APP_INIT_RESET 0x028 #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 #define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) -- 2.49.0
