Hi Krzysztof,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Sent: 12 July 2025 01:46 PM
> To: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>; vkoul@xxxxxxxxxx;
> kishon@xxxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx;
> conor+dt@xxxxxxxxxx; alim.akhtar@xxxxxxxxxxx; andre.draszik@xxxxxxxxxx;
> peter.griffin@xxxxxxxxxx; neil.armstrong@xxxxxxxxxx; kauschluss@xxxxxxxxxxx;
> ivo.ivanov.ivanov1@xxxxxxxxx; m.szyprowski@xxxxxxxxxxx;
> s.nawrocki@xxxxxxxxxxx
> Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-samsung-
> soc@xxxxxxxxxxxxxxx; rosa.pila@xxxxxxxxxxx; dev.tailor@xxxxxxxxxxx;
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> Subject: Re: [PATCH v4 2/6] phy: exynos5-usbdrd: support HS phy for
> ExynosAutov920
>
> On 01/07/2025 14:07, Pritam Manohar Sutar wrote:
> > This SoC has a single USB 3.1 DRD combo phy that supports both
> > UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers
> > those only support the UTMI+ (HS) interface.
> >
> > Support only UTMI+ port for this SoC which is very similar to what the
> > existing Exynos850 supports.
> >
> > This SoC shares phy isol between USBs. Bypass PHY isol when first USB
> > is powered on and enable it when all of then are powered off. Add
> > required change in phy driver to support HS phy for this SoC.
> >
> > Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
>
> Drop
Sure.
>
> You again added significant changes and claimed they were reviewed.
>
> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
> > ---
> > drivers/phy/samsung/phy-exynos5-usbdrd.c | 131 ++++++++++++++++++++
> > include/linux/soc/samsung/exynos-regs-pmu.h | 2 +
> > 2 files changed, 133 insertions(+)
> >
> > diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > index dd660ebe8045..64f3316f6ad4 100644
> > --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > @@ -480,6 +480,8 @@ struct exynos5_usbdrd_phy {
> > enum typec_orientation orientation;
> > };
> >
> > +static atomic_t usage_count = ATOMIC_INIT(0);
Presently, existed SoC in driver, supports only one USB port and
it does not have any complications to handle shared isol. However,
phy isols are shared across USB20s in ExynosAutov920
(here ExynosAutov920 has 4 ports with shared phy isols). phy isol
should be enabled when all ports are disabled else bypassed if any
one of usbs is in use. phy isol is handled at bootloader in Downstream code.
USB20 ports won't work if isol is not handled in any bootloader. Hence,
added usage_count for the purpose.
But still, it depends on phy isol architecture, if SoC shares phy isol with
USBs or it can have separate phy isols for each usbs.
>
> No, you cannot have singletons. How are you going to handle two independent
> phys?
Agreed with your point and have to handle shared and separate isols in same driver.
We will take this later in subsequent patch-sets.
For now, will remove this usage_count and bring up only basic support for ExynosAutov920 phy.
>
> Best regards,
> Krzysztof
Thank you.
Regards,
Pritam
