On 01/07/2025 14:07, Pritam Manohar Sutar wrote:
> This SoC has a single USB 3.1 DRD combo phy that supports both
> UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers
> those only support the UTMI+ (HS) interface.
>
> Support only UTMI+ port for this SoC which is very similar to what
> the existing Exynos850 supports.
>
> This SoC shares phy isol between USBs. Bypass PHY isol when first USB
> is powered on and enable it when all of then are powered off. Add
> required change in phy driver to support HS phy for this SoC.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
Drop
You again added significant changes and claimed they were reviewed.
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 131 ++++++++++++++++++++
> include/linux/soc/samsung/exynos-regs-pmu.h | 2 +
> 2 files changed, 133 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index dd660ebe8045..64f3316f6ad4 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -480,6 +480,8 @@ struct exynos5_usbdrd_phy {
> enum typec_orientation orientation;
> };
>
> +static atomic_t usage_count = ATOMIC_INIT(0);
No, you cannot have singletons. How are you going to handle two
independent phys?
Best regards,
Krzysztof
