On 06/05/2025 10:01, Pritam Manohar Sutar wrote:
> clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
> It shows 400Mhz instead of 40Mhz as below.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
>
> Correct the clk_tree by adding correct clock parent for
> "mout_hsi1_usbdrd_user".
>
> Post this change, clk_summary shows correct value.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
>
> Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC")
> Cc: stable <stable@xxxxxxxxxx>
Run checkpatch BEFORE you send the patches.
WARNING: Invalid email format for stable: 'stable <stable@xxxxxxxxxx>',
prefer 'stable@xxxxxxxxxx'
Best regards,
Krzysztof
