Hi Pritam
> -----Original Message-----
> From: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
> Sent: Tuesday, May 6, 2025 1:32 PM
> To: krzk@xxxxxxxxxx; s.nawrocki@xxxxxxxxxxx; cw00.choi@xxxxxxxxxxx;
> alim.akhtar@xxxxxxxxxxx; mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx;
> sunyeal.hong@xxxxxxxxxxx
> Cc: linux-samsung-soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; linux-
> arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> rosa.pila@xxxxxxxxxxx; dev.tailor@xxxxxxxxxxx;
> faraz.ata@xxxxxxxxxxx; Pritam Manohar Sutar
> <pritam.sutar@xxxxxxxxxxx>; stable <stable@xxxxxxxxxx>
> Subject: [PATCH v2] clk: samsung: correct clock summary for hsi1 block
>
> clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
> It shows 400Mhz instead of 40Mhz as below.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
>
> Correct the clk_tree by adding correct clock parent for
> "mout_hsi1_usbdrd_user".
>
> Post this change, clk_summary shows correct value.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
>
> Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto
> v920 SoC")
> Cc: stable <stable@xxxxxxxxxx>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
