Hi Sebastian, On 17.06.25 12:00, Sebastian Andrzej Siewior wrote:
Even if CPU1 would handle CPU0's timers then it would wake cyclictest on CPU0 but that thread would have to wake until CPU0 is done with the PCI bus. CPU1 knows nothing about it.
Okay then the latency I see on the other CPU must be from a PCI access done by the second CPU which stall on the same shared bus.
Anyway: Thanks for your help Sebastian! I can probably live well with these spikes in latency. I was more concerned that there is a deeper issue with my config and the response time could be unbounded.
Marc
