On 2025-06-17 12:03:31 [+0200], Marc Strämke wrote: > Hi Sebastian, Hi, > On 17.06.25 12:00, Sebastian Andrzej Siewior wrote: > > Even if CPU1 would handle CPU0's timers then it would wake cyclictest on > > CPU0 but that thread would have to wake until CPU0 is done with the PCI > > bus. CPU1 knows nothing about it. > > Okay then the latency I see on the other CPU must be from a PCI access done > by the second CPU which stall on the same shared bus. Okay. > > Anyway: Thanks for your help Sebastian! I can probably live well with these > spikes in latency. I was more concerned that there is a deeper issue with my > config and the response time could be unbounded. You don't have to live with it. You could add a read after the writes in the loop (wrfl()). This should help. Some Intel CPUs have a MSR bit to disable this kind of caching on the PCI bus. Maybe the AMD CPU has this, too. Or there might be a switch in the BIOS. > Marc Sebastian
