On Thu, 15 May 2025 at 16:18, Thierry Bultel
<thierry.bultel.yh@xxxxxxxxxxxxxx> wrote:
> RZ/T2H has 2 register blocks at different addresses.
>
> The clock tree has configurable dividers and mux selectors.
> Add these new clock types, new register layout type, and
> registration code for mux and div in registration callback.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> ---
> Changes v8->v9:
> - Renamed r9a09g077-cpg-mssr.c to r9a09g077-cpg.c
> - Makefile: keep alphabetical order
> - Fixed DIVSCI0ASYNC
> - Removed unused CLK_MAIN
> - Simplified the clock tree, removing CLK_SEL_PLL0, CLK_SEL_PLL1 & CLK_SEL_PLL4
> - Renamed loco to .loco
> - Fixed the register bits in dtable_24_25_30_32, re-ordered the table
> - DEF_DIV & DEF_MUX: set flag to zero always (might change in a future commit)
> - Do not set CLK_DIVIDER_HIWORD_MASK
> - Uses '8' as value of removed R9A09G077_PCLK_SCI0 definition
> - Fixed addr calculation with RZT2H_REG_OFFSET in r9a09g077_cpg_clk_register
> - struct cpg_core_clk: moved union in specific section
> - Renamed cpg_read_rzt2h_mstp to cpg_rzt2h_mstp_read
> - Renamed cpg_write_rzt2h_mstp to cpg_rzt2h_mstp_write
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
