Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
to improve compatibility with a wider range of I2C peripherals. The previous
1MHz setting was too aggressive for some devices on the bus, which experienced
timing issues at such a frequency.
Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 43d79158d81a..ecea29a76b14 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -85,7 +85,7 @@ &gpu {
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
- clock-frequency = <1000000>;
+ clock-frequency = <400000>;
status = "okay";
raa215300: pmic@12 {
--
2.43.0
