On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
Document 'aux' clock which are used to supply the PCIe bus. This
is useful in case of a hardware setup, where the PCIe controller
input clock and the PCIe bus clock are supplied from the same
clock synthesiser, but from different differential clock outputs:
How different is this clock from the 'reference clock'? I'm not sure what you
mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
and the binding already has 'ref' clock for that purpose. So I don't understand
how this new clock is connected to the endpoint device.
See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the
controller side, CLK_DIF1 is the bus (or 'aux') clock which feeds the
bus (or endpoint) side. Both clock come from the same clock synthesizer,
but from two separate clock outputs of the synthesizer.
____________ _____________
| R-Car PCIe | | PCIe device |
| | | |
| PCIe RX<|==================|>PCIe TX |
| PCIe TX<|==================|>PCIe RX |
| | | |
| PCIe CLK<|======.. ..======|>PCIe CLK |
'------------' || || '-------------'
|| ||
____________ || ||
| 9FGV0441 | || ||
| | || ||
| CLK DIF0<|======'' ||
| CLK DIF1<|==========''
| CLK DIF2<|
| CLK DIF3<|
'------------'
