Hi Prabhakar,
On Fri, 9 May 2025 at 15:29, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> On Thu, May 8, 2025 at 5:13 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Mon, 28 Apr 2025 at 20:42, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > used as clock sources for the GBETH IP.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > v2->v3:
> > > - Used DEF_MOD_MUX_EXTERNAL() macro for external MUX clocks.
> > > - Renamed gbe0/1 external mux clock names
> >
> > Thanks for the update!
> >
> > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> > > {0, 0},
> > > };
> > >
> > > +static const struct clk_div_table dtable_2_100[] = {
> > > + {0, 2},
> > > + {1, 10},
> > > + {2, 100},
> > > + {0, 0},
> > > +};
> > > +
> > > +/* Mux clock tables */
> > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
> > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
> > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
> > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
> > > +
> > > static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> > > /* External Clock Inputs */
> > > DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
> >
> > This patch starts to LGTM. The only outstanding issue is how the
> > et*_[rt]xclk will be provided. I have read your comments on v2,
> > and am eagerly awaiting the full patch set (CPG binding update, PHY
> > updates, ...) to get this all to work.
> >
> My intention here is to get these initial patches in so that we have
> Ethernet working on RZ/V2H (G3E/V2N) so that we have these boards on
> LAVA and tackle et*_[rt]xclk clocks for the next cycle as this will
> have to be discussed the -net maintainers. Are you OK with this
> approach.
You mean that (1) Ethernet works with just series
- "[PATCH v4 0/2] clk: renesas: Skip monitor checks for external
clocks and add clocks for GBETH"[1] and
- "[PATCH v2 0/2] arm64: dts: renesas: Add GBETH support to R9A09G057
SoC[2]"
applied, without any extra additions to define the et*_[rt]xclk clocks,
and (2) you see a clear path forward that can stay backwards compatible
with the DTS from [2]?
If that is the case, then I think we can move forward with these series.
Thanks!
[1] https://lore.kernel.org/20250509160121.331073-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
[2] https://lore.kernel.org/20250509153559.326603-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
