The original driver used magic-number offsets because the register names
were unknown. Now most of the register names have been disclosed.
Signed-off-by: Michael Dege <michael.dege@xxxxxxxxxxx>
---
drivers/phy/renesas/renesas-ether-serdes.c | 298 ++++++++++++++-------
1 file changed, 203 insertions(+), 95 deletions(-)
diff --git a/drivers/phy/renesas/renesas-ether-serdes.c b/drivers/phy/renesas/renesas-ether-serdes.c
index 4c53c81903ef..81b67880678b 100644
--- a/drivers/phy/renesas/renesas-ether-serdes.c
+++ b/drivers/phy/renesas/renesas-ether-serdes.c
@@ -23,6 +23,55 @@
#define RENESAS_ETH_SERDES_LOCAL_OFFSET 0x2600
#define RENESAS_ETH_SERDES_NUM_RETRY_LINKUP 3
+#define BANK_180 0x0180
+#define VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0 0x00c0
+#define VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1 0x00c4
+#define VR_XS_PMA_MP_12G_16G_TX_GENCTRL2 0x00c8
+#define VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL 0x00d0
+#define VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0 0x00d8
+#define VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1 0x00dc
+#define VR_XS_PMA_MP_12G_16G_25G_TX_STS 0x0100
+#define VR_XS_PMA_MP_12G_16G_25G_RX_STS 0x0180
+#define VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1 0x0144
+#define VR_XS_PMA_MP_12G_16G_RX_GENCTRL2 0x0148
+#define VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL 0x0150
+#define VR_XS_PMA_MP_12G_RX_EQ_CTRL0 0x0160
+#define VR_XS_PMA_MP_12G_AFE_DFE_EN_CTRL 0x0174
+#define VR_XS_PMA_CONSUMER_10G_RX_GENCTRL4 0x01a0
+#define VR_XS_PMA_MP_10G_RX_IQ_CTRL0 0x01ac
+#define VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL 0x01c0
+#define VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0 0x01c4
+#define VR_XS_PMA_MP_12G_MPLLA_CTRL1 0x01c8
+#define VR_XS_PMA_MP_10G_MPLLA_CTRL2 0x01cc
+#define VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0 0x01d0
+#define VR_XS_PMA_MP_12G_MPLLB_CTRL1 0x01d4
+#define VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2 0x01d8
+#define VR_XS_PMA_MP_12G_MPLLA_CTRL3 0x01dc
+#define VR_XS_PMA_MP_12G_MPLLB_CTRL3 0x01e0
+#define VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL 0x0244
+#define VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0 0x0248
+#define VR_XS_PMA_MP_12G_VCO_CAL_REF0 0x0258
+#define VR_XS_PMA_MP_12G_16G_25G_SRAM 0x026c
+
+#define BANK_300 0x0300
+#define SR_XS_PCS_CTRL1 0x0000
+#define SR_XS_PCS_STS1 0x0004
+#define SR_XS_PCS_CTRL2 0x001c
+
+#define BANK_380 0x0380
+#define VR_XS_PCS_DIG_CTRL1 0x0000
+#define VR_XS_PCS_DEBUG_CTRL 0x0014
+#define VR_XS_PCS_KR_CTRL 0x001c
+#define VR_XS_PCS_SFTY_UE_INTRO 0x03c0
+#define VR_XS_PCS_SFTY_DISABLE 0x03d0
+
+#define BANK_1F00 0x1f00
+#define SR_MII_CTRL 0x0000
+
+#define BANK_1F80 0x1f80
+#define VR_MII_DIG_CTRL1 0x0000
+#define VR_MII_EEE_TXTIMER 0x0008
+
struct renesas_eth_serdes_drv_data;
struct renesas_eth_serdes_channel {
struct renesas_eth_serdes_drv_data *dd;
@@ -97,12 +146,13 @@ renesas_eth_serdes_common_init_ram(struct renesas_eth_serdes_drv_data *dd)
for (i = 0; i < dd->info->renesas_eth_serdes_num; i++) {
channel = &dd->channel[i];
- ret = renesas_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_25G_SRAM,
+ BANK_180, BIT(0), 0x01);
if (ret)
return ret;
}
- renesas_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_16G_25G_SRAM, BANK_180, 0x03);
return ret;
}
@@ -113,15 +163,16 @@ renesas_eth_serdes_common_setting(struct renesas_eth_serdes_channel *channel)
struct renesas_eth_serdes_drv_data *dd = channel->dd;
/* Set combination mode */
- renesas_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7);
- renesas_eth_serdes_write32(dd->addr, 0x01cc, 0x180, 0xc200);
- renesas_eth_serdes_write32(dd->addr, 0x01c4, 0x180, 0x0042);
- renesas_eth_serdes_write32(dd->addr, 0x01c8, 0x180, 0);
- renesas_eth_serdes_write32(dd->addr, 0x01dc, 0x180, 0x002f);
- renesas_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
- renesas_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
- renesas_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
- renesas_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, BANK_180, 0xd7);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_10G_MPLLA_CTRL2, BANK_180, 0xc200);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0, BANK_180, 0x42);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_MPLLA_CTRL1, BANK_180, 0);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_MPLLA_CTRL3, BANK_180, 0x2f);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0, BANK_180, 0x60);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2, BANK_180, 0x2200);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_MPLLB_CTRL1, BANK_180, 0);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PMA_MP_12G_MPLLB_CTRL3, BANK_180, 0x3d);
+
return 0;
}
@@ -130,88 +181,130 @@ renesas_eth_serdes_chan_setting(struct renesas_eth_serdes_channel *channel)
{
int ret;
+
switch (channel->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2000);
- renesas_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0011);
- renesas_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x0540);
- renesas_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
- renesas_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0000);
- renesas_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0002);
- renesas_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0003);
- renesas_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0100);
- renesas_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0100);
- renesas_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
- renesas_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0007);
- renesas_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
- renesas_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
- renesas_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0101);
- ret = renesas_eth_serdes_reg_wait(channel, 0x00c8, 0x0180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2000);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
+ BANK_180, 0x11);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0,
+ BANK_180, 0x540);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_VCO_CAL_REF0,
+ BANK_180, 0x15);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, 0x100);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_CONSUMER_10G_RX_GENCTRL4,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL,
+ BANK_180, 0x02);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL,
+ BANK_180, 0x03);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, 0x100);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, 0x100);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_AFE_DFE_EN_CTRL,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_RX_EQ_CTRL0,
+ BANK_180, 0x07);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_10G_RX_IQ_CTRL0,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
+ BANK_180, 0x310);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, 0x101);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0101);
- ret = renesas_eth_serdes_reg_wait(channel, 0x0148, 0x0180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, 0x101);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
- renesas_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
- renesas_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
- renesas_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0001);
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2100);
- ret = renesas_eth_serdes_reg_wait(channel, 0x0000, 0x0380, BIT(8), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
+ BANK_180, 0x1310);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0,
+ BANK_180, 0x1800);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, SR_XS_PCS_CTRL2, BANK_300, 0x01);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2100);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PCS_DIG_CTRL1,
+ BANK_380, BIT(8), 0);
if (ret)
return ret;
if (channel->speed == 1000)
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0140);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x140);
else if (channel->speed == 100)
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2100);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x2100);
/* For AN_ON */
- renesas_eth_serdes_write32(channel->addr, 0x0004, 0x1f80, 0x0005);
- renesas_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
+ renesas_eth_serdes_write32(channel->addr, 0x0004, BANK_1F80, 0x0005);
+ renesas_eth_serdes_write32(channel->addr, 0x0028, BANK_1F80, 0x07a1);
+ renesas_eth_serdes_write32(channel->addr, VR_MII_DIG_CTRL1, BANK_1F80, 0x0208);
break;
case PHY_INTERFACE_MODE_USXGMII:
case PHY_INTERFACE_MODE_5GBASER:
- renesas_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0);
- renesas_eth_serdes_write32(channel->addr, 0x0014, 0x380, 0x50);
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2200);
- renesas_eth_serdes_write32(channel->addr, 0x001c, 0x380, 0x400);
- renesas_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x1);
- renesas_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x56a);
- renesas_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x15);
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x1100);
- renesas_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 1);
- renesas_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x01);
- renesas_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x01);
- renesas_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x300);
- renesas_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x300);
- renesas_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0);
- renesas_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x4);
- renesas_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0);
- renesas_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x310);
- renesas_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0301);
- ret = renesas_eth_serdes_reg_wait(channel, 0x00c8, 0x180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, SR_XS_PCS_CTRL2, BANK_300, 0x0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_DEBUG_CTRL, BANK_380, 0x50);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2200);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_KR_CTRL, BANK_380, 0x400);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
+ BANK_180, 0x1);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0,
+ BANK_180, 0x56a);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_VCO_CAL_REF0,
+ BANK_180, 0x15);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, 0x1100);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_CONSUMER_10G_RX_GENCTRL4,
+ BANK_180, 1);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL,
+ BANK_180, 0x01);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL,
+ BANK_180, 0x01);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, 0x300);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, 0x300);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_AFE_DFE_EN_CTRL,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_RX_EQ_CTRL0,
+ BANK_180, 0x4);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_10G_RX_IQ_CTRL0,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
+ BANK_180, 0x310);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, 0x0301);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x301);
- ret = renesas_eth_serdes_reg_wait(channel, 0x0148, 0x180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, 0x301);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
- renesas_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
- renesas_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0);
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2300);
- ret = renesas_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(8), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
+ BANK_180, 0x1310);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0,
+ BANK_180, 0x1800);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1,
+ BANK_180, 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2300);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PCS_DIG_CTRL1,
+ BANK_380, BIT(8), 0);
if (ret)
return ret;
break;
-
default:
return -EOPNOTSUPP;
}
@@ -228,19 +321,20 @@ renesas_eth_serdes_chan_speed(struct renesas_eth_serdes_channel *channel)
case PHY_INTERFACE_MODE_SGMII:
/* For AN_ON */
if (channel->speed == 1000)
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x1140);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x1140);
else if (channel->speed == 100)
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x3100);
- ret = renesas_eth_serdes_reg_wait(channel, 0x0008, 0x1f80, BIT(0), 1);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x3100);
+ ret = renesas_eth_serdes_reg_wait(channel, VR_MII_EEE_TXTIMER,
+ BANK_1F80, BIT(0), 1);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
+ renesas_eth_serdes_write32(channel->addr, VR_MII_EEE_TXTIMER, BANK_1F80, 0x0000);
break;
case PHY_INTERFACE_MODE_USXGMII:
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x120);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x120);
break;
case PHY_INTERFACE_MODE_5GBASER:
- renesas_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2120);
+ renesas_eth_serdes_write32(channel->addr, SR_MII_CTRL, BANK_1F00, 0x2120);
break;
default:
return -EOPNOTSUPP;
@@ -255,14 +349,17 @@ static int renesas_eth_serdes_monitor_linkup(struct renesas_eth_serdes_channel *
int i, ret;
for (i = 0; i < RENESAS_ETH_SERDES_NUM_RETRY_LINKUP; i++) {
- ret = renesas_eth_serdes_reg_wait(channel, 0x0004, 0x300, BIT(2), BIT(2));
+ ret = renesas_eth_serdes_reg_wait(channel, SR_XS_PCS_STS1,
+ BANK_300, BIT(2), BIT(2));
if (!ret)
break;
/* restart */
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, 0x0100);
udelay(1);
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0000);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, 0x0000);
}
return ret;
@@ -292,30 +389,31 @@ static int renesas_eth_serdes_hw_init(struct renesas_eth_serdes_channel *channel
return ret;
for (i = 0; i < dd->info->renesas_eth_serdes_num; i++) {
- ret = renesas_eth_serdes_reg_wait(&dd->channel[i], 0x0000,
- 0x300, BIT(15), 0);
+ ret = renesas_eth_serdes_reg_wait(&dd->channel[i], SR_XS_PCS_CTRL1,
+ BANK_300, BIT(15), 0);
if (ret)
return ret;
}
for (i = 0; i < dd->info->renesas_eth_serdes_num; i++)
- renesas_eth_serdes_write32(dd->channel[i].addr, 0x03d4, 0x380, 0x0443);
+ renesas_eth_serdes_write32(dd->channel[i].addr, 0x03d4, BANK_380, 0x0443);
ret = renesas_eth_serdes_common_setting(channel);
if (ret)
return ret;
for (i = 0; i < dd->info->renesas_eth_serdes_num; i++)
- renesas_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0001);
-
+ renesas_eth_serdes_write32(dd->channel[i].addr, VR_XS_PCS_SFTY_DISABLE,
+ BANK_380, 0x0001);
- renesas_eth_serdes_write32(dd->addr, 0x0000, 0x380, 0x8000);
+ renesas_eth_serdes_write32(dd->addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x8000);
ret = renesas_eth_serdes_common_init_ram(dd);
if (ret)
return ret;
- return renesas_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
+ return renesas_eth_serdes_reg_wait(&dd->channel[0], VR_XS_PCS_DIG_CTRL1,
+ BANK_380, BIT(15), 0);
}
static int renesas_eth_serdes_init(struct phy *p)
@@ -353,27 +451,37 @@ static int renesas_eth_serdes_hw_init_late(struct renesas_eth_serdes_channel
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_SFTY_UE_INTRO, BANK_380, 0x0000);
- renesas_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PCS_SFTY_DISABLE, BANK_380, 0x0000);
- val = renesas_eth_serdes_read32(channel->addr, 0x00c0, 0x180);
- renesas_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val | BIT(8));
- ret = renesas_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 1);
+ val = renesas_eth_serdes_read32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
+ BANK_180);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
+ BANK_180, val | BIT(8));
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_25G_TX_STS,
+ BANK_180, BIT(0), 1);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val &= ~BIT(8));
- ret = renesas_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
+ BANK_180, val &= ~BIT(8));
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_25G_TX_STS,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
- val = renesas_eth_serdes_read32(channel->addr, 0x0144, 0x180);
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, val | BIT(4));
- ret = renesas_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 1);
+ val = renesas_eth_serdes_read32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, val | BIT(4));
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_25G_RX_STS,
+ BANK_180, BIT(0), 1);
if (ret)
return ret;
- renesas_eth_serdes_write32(channel->addr, 0x0144, 0x180, val &= ~BIT(4));
- ret = renesas_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 0);
+ renesas_eth_serdes_write32(channel->addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1,
+ BANK_180, val &= ~BIT(4));
+ ret = renesas_eth_serdes_reg_wait(channel, VR_XS_PMA_MP_12G_16G_25G_RX_STS,
+ BANK_180, BIT(0), 0);
if (ret)
return ret;
--
2.34.1
________________________________
Renesas Electronics Europe GmbH
Registered Office: Arcadiastrasse 10
DE-40472 Duesseldorf
Commercial Registry: Duesseldorf, HRB 3708
Managing Director: Carsten Jauch
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Tax-ID-No: 105/5839/1793
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