Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
---
Changes v7->v8:
- extra parenthesis
- added loco
- renesas-cpg-mssr.h: removed unused clocks, added a macro for mstp
Changes v6->v7:
- Add description for reg property
Changes v5->v6:
- Set clock minItem constraint
- Moved additionalProperties after 'allOf' section
Changes v4->v5:
- Set reg minItems and maxItems defaults at top level
Changes v3->v4:
- Handle maxItems and clocks names properly in schema.
---
.../bindings/clock/renesas,cpg-mssr.yaml | 58 ++++++++++++++-----
.../clock/renesas,r9a09g077-cpg-mssr.h | 48 +++++++++++++++
2 files changed, 90 insertions(+), 16 deletions(-)
create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 77ce3615c65a..464827f2067e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -52,9 +52,15 @@ properties:
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
+ - renesas,r9a09g077-cpg-mssr # RZ/T2H
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: base address of register block 0
+ - description: base address of register block 1
+ description: base addresses of clock controller. Some controllers
+ (like r9a09g077) use two blocks instead of a single one.
clocks:
minItems: 1
@@ -63,11 +69,6 @@ properties:
clock-names:
minItems: 1
maxItems: 2
- items:
- enum:
- - extal # All
- - extalr # Most R-Car Gen3 and RZ/G2
- - usb_extal # Most R-Car Gen2 and RZ/G1
'#clock-cells':
description: |
@@ -92,16 +93,6 @@ properties:
the datasheet.
const: 1
-if:
- not:
- properties:
- compatible:
- items:
- enum:
- - renesas,r7s9210-cpg-mssr
-then:
- required:
- - '#reset-cells'
required:
- compatible
@@ -111,6 +102,41 @@ required:
- '#clock-cells'
- '#power-domain-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-cpg-mssr
+ then:
+ properties:
+ reg:
+ minItems: 2
+ clock-names:
+ items:
+ - const: extal
+ else:
+ properties:
+ reg:
+ maxItems: 1
+ clock-names:
+ items:
+ enum:
+ - extal # All
+ - extalr # Most R-Car Gen3 and RZ/G2
+ - usb_extal # Most R-Car Gen2 and RZ/G1
+
+ - if:
+ not:
+ properties:
+ compatible:
+ items:
+ enum:
+ - renesas,r7s9210-cpg-mssr
+ then:
+ required:
+ - '#reset-cells'
+
additionalProperties: false
examples:
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
new file mode 100644
index 000000000000..d5b16d08e75d
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CLK_CA55C0 0
+#define R9A09G077_CLK_CA55C1 1
+#define R9A09G077_CLK_CA55C2 2
+#define R9A09G077_CLK_CA55C3 3
+#define R9A09G077_CLK_CA55S 4
+#define R9A09G077_CLK_CR52_CPU0 5
+#define R9A09G077_CLK_CR52_CPU1 6
+#define R9A09G077_CLK_BSC 7
+#define R9A09G077_CLK_CKIO R9A09G077_CLK_BSC
+#define R9A09G077_CLK_PCLKAH 8
+#define R9A09G077_CLK_PCLKAM 9
+#define R9A09G077_CLK_PCLKAL 10
+#define R9A09G077_CLK_PCLKGPTL 11
+#define R9A09G077_CLK_PCLKH 12
+#define R9A09G077_CLK_PCLKM 13
+
+
+#define R9A09G077_MSTPCRA 0
+#define R9A09G077_MSTPCRB 1
+#define R9A09G077_MSTPCRC 2
+#define R9A09G077_MSTPCRD 3
+#define R9A09G077_MSTPCRE 4
+#define R9A09G077_MSTPCRG 7
+#define R9A09G077_MSTPCRI 8
+#define R9A09G077_MSTPCRJ 9
+#define R9A09G077_MSTPCRK 10
+#define R9A09G077_MSTPCRL 11
+#define R9A09G077_MSTPCRM 12
+#define R9A09G077_MSTPCRN 13
+
+#define R9A09G077_MSTP(mstp, idx) (100*(mstp)+(idx))
+
+/* R9A09G077 CPG Module Clocks */
+#define R9A09G077_PCLK_SCI0 R9A09G077_MSTP(R9A09G077_MSTPCRA, 8)
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
+
--
2.43.0
