Hi Mike, Stephen,
The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.16-tag1
for you to fetch changes up to 93f2878136262e6efcc6320bc31ada62fb0afd20:
clk: renesas: r9a09g057: Add clock and reset entries for USB2 (2025-04-22 11:38:28 +0200)
----------------------------------------------------------------
clk: renesas: Updates for v6.16
- Add GPU and USB2 clocks and resets on RZ/V2H(P),
- Add support for the RZ/V2N (R9A09G056) SoC,
- Add GPU clocks and resets on RZ/G3E,
- Miscellaneous fixes and improvements.
Note that this includes a DT binding definition update for the RZ/V2H(P)
SoC, and DT bindings and bindings definitions for the RZ/V2N SoC, which
are shared by the clock driver and DT source files.
Thanks for pulling!
----------------------------------------------------------------
Biju Das (2):
clk: renesas: rzv2h: Fix a typo
clk: renesas: rzv2h: Support static dividers without RMW
Geert Uytterhoeven (2):
Merge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-clk-for-v6.16
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Lad Prabhakar (17):
clk: renesas: rzv2h: Refactor PLL configuration handling
clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`
clk: renesas: rzv2h: Add support for enabling PLLs
clk: renesas: rzv2h: Rename PLL field macros for consistency
clk: renesas: r9a09g057: Add clock and reset entries for GE3D
dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
clk: renesas: rzv2h: Sort compatible list based on SoC part number
clk: renesas: rzv2h: Add support for RZ/V2N SoC
clk: renesas: rzv2h: Add support for static mux clocks
clk: renesas: rzv2h: Add macro for defining static dividers
clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
clk: renesas: r9a09g057: Add clock and reset entries for USB2
Tommaso Merciai (3):
clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()
clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
clk: renesas: r9a09g047: Add clock and reset entries for GE3D
.../bindings/clock/renesas,rzv2h-cpg.yaml | 5 +-
.../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +
.../soc/renesas/renesas,r9a09g057-sys.yaml | 1 +
.../devicetree/bindings/soc/renesas/renesas.yaml | 15 ++
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a09g047-cpg.c | 13 +-
drivers/clk/renesas/r9a09g056-cpg.c | 152 +++++++++++++++++
drivers/clk/renesas/r9a09g057-cpg.c | 36 +++-
drivers/clk/renesas/rzv2h-cpg.c | 186 +++++++++++++++------
drivers/clk/renesas/rzv2h-cpg.h | 87 +++++++++-
include/dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 +++
include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 +
13 files changed, 467 insertions(+), 64 deletions(-)
create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c
create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
