> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: mercredi 23 avril 2025 09:19
> To: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> Cc: thierry.bultel@xxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx; Paul
> Barker <paul.barker.ct@xxxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx;
> linux-clk@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC
>
> Hi Thierry,
Hi Geert,
>
> On Fri, 18 Apr 2025 at 23:22, Thierry Bultel
> <thierry.bultel.yh@xxxxxxxxxxxxxx> wrote:
> > +};
> > > > +
> > > > +static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =
> {
> > > > + DEF_MOD("sci0", 108, R9A09G077_PCLKM),
> > >
> > > Shouldn't that be 8 instead of 108?
> > > Using R9A09G077_PCLKM as the parent is a temporary simplification,
> right?
> >
> > I am probably missing something, isn’t PCKML actually the parent clock ?
>
> According to Figure 7.1 ("Block diagram of clock generation circuit"), it
> is PCLKSCI0, which can be switched to PCLKM. I guess that is the default,
> hence my "temporary simplification" question.
>
> As the actual switching is controlled through the SCI's CCR3 register, the
> SCI block should have two clock inputs in DT (PCLKM and PCLKSCIn), and
> thus the DT bindings should be amended. See also Figure 33.1 ("SCI block
> diagram").
>
Thanks for clarifying.
Indeed, this is the default setting (and the one we have at this stage).
I think that support for PCLKSCIn can be added at the time we support
baudrate setting.
Thierry
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
