Hi Thierry,
On Thu, 3 Apr 2025 at 23:30, Thierry Bultel
<thierry.bultel.yh@xxxxxxxxxxxxxx> wrote:
> Define a new RSCI port type, and the RSCI 32 bits registers set.
> The RZ/T2H SCI has a a fifo, and a quite different set of registers
> from the orginal SH SCI ones.
> DMA is not supported yet.
>
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> ---
> Changes v6->v7:
> - Renamed compatible string to r9a09g077-rsci
Thanks for the update!
Just some cosmetic comments...
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -675,6 +675,13 @@ config SERIAL_SH_SCI_DMA
> depends on SERIAL_SH_SCI && DMA_ENGINE
> default ARCH_RENESAS
>
> +config SERIAL_RSCI
> + tristate "Support for Renesas RZ/T2H SCI variant"
> + depends on SERIAL_SH_SCI
> + help
> + Support for the RZ/T2H SCI variant with fifo.
FIFO
> + Say Y if you want to be able to use the RZ/T2H SCI serial port.
> +
> config SERIAL_HS_LPC32XX
> tristate "LPC32XX high speed serial port support"
> depends on ARCH_LPC32XX || COMPILE_TEST
> --- /dev/null
> +++ b/drivers/tty/serial/rsci.c
> +static u32 rzsci_serial_in(struct uart_port *p, int offset)
rsci_* (everywhere)
> +{
> + return readl(p->membase + offset);
> +}
> +static void rzsci_prepare_console_write(struct uart_port *port, u32 ctrl)
> +{
> + struct sci_port *s = to_sci_port(port);
> + u32 ctrl_temp =
> + s->params->param_bits->rxtx_enable |
> + CCR0_TIE |
> + s->hscif_tot;
u32 ctrl_temp = s->params->param_bits->rxtx_enable | CCR0_TIE |
s->hscif_tot;
> + rzsci_serial_out(port, CCR0, ctrl_temp);
> +}
> +static const struct uart_ops rzt2_sci_uart_ops = {
rsci_uart_ops
> + .tx_empty = rzsci_tx_empty,
> + .set_mctrl = rzsci_set_mctrl,
> + .get_mctrl = rzsci_get_mctrl,
> + .start_tx = rzsci_start_tx,
> + .stop_tx = rzsci_stop_tx,
> + .stop_rx = rzsci_stop_rx,
> + .startup = sci_startup,
> + .shutdown = sci_shutdown,
> + .set_termios = rzsci_set_termios,
> + .pm = sci_pm,
> + .type = rzsci_type,
> + .release_port = sci_release_port,
> + .request_port = sci_request_port,
> + .config_port = sci_config_port,
> + .verify_port = sci_verify_port,
> +};
> +
> +static const struct sci_port_ops rzsci_port_ops = {
rsci_port_ops
> + .read_reg = rzsci_serial_in,
> + .write_reg = rzsci_serial_out,
> + .clear_SCxSR = rzsci_clear_SCxSR,
> + .transmit_chars = rzsci_transmit_chars,
> + .receive_chars = rzsci_receive_chars,
> + .poll_put_char = rzsci_poll_put_char,
> + .prepare_console_write = rzsci_prepare_console_write,
> + .suspend_regs_size = rzsci_suspend_regs_size,
> +};
> +
> +struct sci_of_data of_sci_r9a09g077_data = {
of_sci_rsci_data
> + .type = PORT_RSCI,
> + .regtype = SCIx_RZT2H_SCI_REGTYPE,
> + .ops = &rzsci_port_ops,
> + .uart_ops = &rzt2_sci_uart_ops,
> + .params = &rzsci_port_params,
> +};
> +
> +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
> +
> +static int __init rzt2hsci_early_console_setup(struct earlycon_device *device,
> + const char *opt)
rsci_early_console_setup
> +{
> + return scix_early_console_setup(device, &of_sci_r9a09g077_data);
> +}
> +
> +OF_EARLYCON_DECLARE(rzsci, "renesas,r9a09g077-rsci", rzt2hsci_early_console_setup);
> +
> +#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> --- a/include/linux/serial_sci.h
> +++ b/include/linux/serial_sci.h
> @@ -38,6 +38,7 @@ enum {
> SCIx_HSCIF_REGTYPE,
> SCIx_RZ_SCIFA_REGTYPE,
> SCIx_RZV2H_SCIF_REGTYPE,
> + SCIx_RZT2H_SCI_REGTYPE,
SCIx_RSCI_REGTYPE?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
