On Wed, Apr 9, 2025 at 2:08 PM Geert Uytterhoeven
<geert+renesas@xxxxxxxxx> wrote:
>
> Refresh the defconfig for Renesas RZ/Five systems:
> - Disable support for the Zbkb ISA extension for bit manipulation
> instructions, as it is not supported by RZ/Five,
> - Drop CONFIG_SCHED_DEBUG=n (removed in commit b52173065e0aad82
> ("sched/debug: Remove CONFIG_SCHED_DEBUG")).
>
> ---
> Not intended for upstream merge.
> To be applied to the topic/renesas-defconfig branch.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> arch/riscv/configs/rzfive_defconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Cheers,
Prabhakar
> diff --git a/arch/riscv/configs/rzfive_defconfig b/arch/riscv/configs/rzfive_defconfig
> index b5462ae3163521d6..e9998a22dee140cd 100644
> --- a/arch/riscv/configs/rzfive_defconfig
> +++ b/arch/riscv/configs/rzfive_defconfig
> @@ -37,6 +37,7 @@ CONFIG_NONPORTABLE=y
> # CONFIG_RISCV_ISA_ZBA is not set
> # CONFIG_RISCV_ISA_ZBB is not set
> # CONFIG_RISCV_ISA_ZBC is not set
> +# CONFIG_RISCV_ISA_ZBKB is not set
> # CONFIG_RISCV_ISA_ZICBOM is not set
> # CONFIG_RISCV_ISA_ZICBOZ is not set
> # CONFIG_RISCV_ISA_VENDOR_EXT_THEAD is not set
> @@ -212,7 +213,6 @@ CONFIG_DEBUG_MEMORY_INIT=y
> CONFIG_SOFTLOCKUP_DETECTOR=y
> CONFIG_WQ_WATCHDOG=y
> CONFIG_WQ_CPU_INTENSIVE_REPORT=y
> -# CONFIG_SCHED_DEBUG is not set
> CONFIG_DEBUG_RT_MUTEXES=y
> CONFIG_DEBUG_SPINLOCK=y
> CONFIG_DEBUG_MUTEXES=y
> --
> 2.43.0
>
>
