From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> Since the sibling data is filled after the priv->clks[] array entry is populated, the first clock that is probed and has a sibling will temporarily behave as its own sibling until its actual sibling is populated. To avoid any issues, skip this clock when searching for a sibling. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> --- drivers/clk/renesas/rzg2l-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b91dfbfb01e3..2ae36d94fbfa 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1324,6 +1324,9 @@ static struct mstp_clock hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]); clk = to_mod_clock(hw); + if (clk == clock) + continue; + if (clock->off == clk->off && clock->bit == clk->bit) return clk; } -- 2.43.0
