The "qcom,acc" and "qcom,saw" properties aren't valid with "spin-table"
enable-method nor are they used on 64-bit kernels, so they can be
dropped.
The "spin-table" enable-method requires "cpu-release-addr" property,
so add a dummy entry. It is assumed the bootloader will fill in the
correct values.
Signed-off-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/msm8939.dtsi | 24 ++++++++----------------
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index 7cd5660de1b3..36f2ba3fb81c 100644
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -46,10 +46,9 @@ cpu0: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x100>;
next-level-cache = <&l2_1>;
- qcom,acc = <&acc0>;
- qcom,saw = <&saw0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
@@ -64,10 +63,9 @@ cpu1: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x101>;
next-level-cache = <&l2_1>;
- qcom,acc = <&acc1>;
- qcom,saw = <&saw1>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
@@ -77,10 +75,9 @@ cpu2: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x102>;
next-level-cache = <&l2_1>;
- qcom,acc = <&acc2>;
- qcom,saw = <&saw2>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
@@ -90,10 +87,9 @@ cpu3: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x103>;
next-level-cache = <&l2_1>;
- qcom,acc = <&acc3>;
- qcom,saw = <&saw3>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
@@ -103,9 +99,8 @@ cpu4: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x0>;
- qcom,acc = <&acc4>;
- qcom,saw = <&saw4>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
@@ -121,10 +116,9 @@ cpu5: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x1>;
next-level-cache = <&l2_0>;
- qcom,acc = <&acc5>;
- qcom,saw = <&saw5>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
@@ -134,10 +128,9 @@ cpu6: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x2>;
next-level-cache = <&l2_0>;
- qcom,acc = <&acc6>;
- qcom,saw = <&saw6>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
@@ -147,10 +140,9 @@ cpu7: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x3>;
next-level-cache = <&l2_0>;
- qcom,acc = <&acc7>;
- qcom,saw = <&saw7>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
--
2.47.2
