RE: [PATCH v6 02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

[Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>]

Hi Rob, 
thanks for your review,

> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > index 77ce3615c65a..dee4c44ef025 100644
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > @@ -52,9 +52,11 @@ properties:
> >        - renesas,r8a779f0-cpg-mssr # R-Car S4-8
> >        - renesas,r8a779g0-cpg-mssr # R-Car V4H
> >        - renesas,r8a779h0-cpg-mssr # R-Car V4M
> > +      - renesas,r9a09g077-cpg-mssr # RZ/T2H
> >
> >    reg:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> 
> You need to define what each entry is. And do that here assuming the first
> entry is the same in either case.

Would this be the right way ? (maxItems become implicit)


  reg:
    minItems: 1
    items:
      - description: base address of register block 0
      - description: base address of register block 1
    description: base addresses of clock controller. Some controllers
      (like r9a09g077) use two blocks instead of a single one).


Thanks !
Thierry