Hi Prabhakar,
On Sun, 30 Mar 2025 at 23:08, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Introduce the `RZ_MIPI_DSI_16BPP` feature flag in `rzg2l_mipi_dsi_hw_info`
> to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
> 16BPP, whereas this feature is missing on the RZ/G2L SoC.
>
> Update the `mipi_dsi_host_attach()` function to check this flag before
> allowing 16BPP formats. If the SoC does not support 16BPP, return an error
> to prevent incorrect format selection.
>
> This change enables finer-grained format support control for different
> SoC variants.
>
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -30,6 +30,8 @@
>
> struct rzg2l_mipi_dsi;
>
> +#define RZ_MIPI_DSI_16BPP BIT(0)
> +
> struct rzg2l_mipi_dsi_hw_info {
> int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz);
> void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
> @@ -38,6 +40,7 @@ struct rzg2l_mipi_dsi_hw_info {
> unsigned long max_dclk;
> unsigned long min_dclk;
> bool has_dphy_rstc;
> + u8 features;
Please settle on a single solution for all features: either use a
boolean flag to indicate 16bpp, or a feature bit to indicate the need
for the DPHY reset signal.
> };
>
> struct rzg2l_mipi_dsi {
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
