Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar <prabhakar.csengg@xxxxxxxxx> > Sent: 30 March 2025 22:07 > Subject: [PATCH 09/17] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication > and division by 8. The updated equation: > > hsfreq = (mode->clock * bpp) / (dsi->lanes); > > produces the same result while improving readability and clarity. > > Additionally, update the comment to clarify the relationship between HS clock bit frequency, HS byte > clock frequency, and HSFREQ. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Cheers, Biju > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz- > du/rzg2l_mipi_dsi.c > index c6f60b7f203b..746f82442c01 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -277,10 +277,10 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > * hsclk: DSI HS Byte clock frequency (Hz) > * lanes: number of data lanes > * > - * hsclk(bit) = hsclk(byte) * 8 > + * hsclk(bit) = hsclk(byte) * 8 = hsfreq > */ > bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); > - hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); > + hsfreq = (mode->clock * bpp) / dsi->lanes; > > ret = pm_runtime_resume_and_get(dsi->dev); > if (ret < 0) > -- > 2.49.0
