From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Hi All, This patch series adds clock and reset entries for USB2 and GBETH in the R9A09G057 SoC. Support for ignoring the monitoring of CLK_MON bits for external clocks is also added and the logic to ensure that module clock is ON now checks both CLK_ON and CLK_MON bits. Also the core clocks for USB2 and GBETH are added in the device tree bindings. Note, these patch apply on top of the following patch series: https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ Cheers, Prabhakar Lad Prabhakar (6): clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: r9a09g057: Add clock and reset entries for USB2 clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1 drivers/clk/renesas/r9a09g057-cpg.c | 92 ++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.c | 36 +++++++- drivers/clk/renesas/rzv2h-cpg.h | 39 +++++++- .../dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 + 4 files changed, 162 insertions(+), 9 deletions(-) -- 2.49.0
