From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.
To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.
Also add `renesas,r9a09g056-pinctrl.h` header file which define pins
that will be used by the driver and board DTS files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++
.../pinctrl/renesas,r9a09g056-pinctrl.h | 30 +++++++++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 768bb3c2b456..5156d54b240b 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -27,6 +27,7 @@ properties:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
- renesas,r9a09g047-pinctrl # RZ/G3E
+ - renesas,r9a09g056-pinctrl # RZ/V2N
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@@ -145,6 +146,7 @@ allOf:
contains:
enum:
- renesas,r9a09g047-pinctrl
+ - renesas,r9a09g056-pinctrl
- renesas,r9a09g057-pinctrl
then:
properties:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
new file mode 100644
index 000000000000..206bba07c288
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2N SoC pinctrl bindings.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
+#define RZV2N_P0 0
+#define RZV2N_P1 1
+#define RZV2N_P2 2
+#define RZV2N_P3 3
+#define RZV2N_P4 4
+#define RZV2N_P5 5
+#define RZV2N_P6 6
+#define RZV2N_P7 7
+#define RZV2N_P8 8
+#define RZV2N_P9 9
+#define RZV2N_PA 10
+#define RZV2N_PB 11
+
+#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
+#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__ */
--
2.49.0
