Re: [PATCH 2/7] arm64: dts: renesas: r8a779a0: Add ISP core function block

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Hi Niklas

On Sat, Mar 15, 2025 at 04:27:03PM +0100, Niklas Söderlund wrote:
> All ISP instances on V3U have both a channel select and core function
> block, describe the core region in addition to the existing cs region.
>
> The interrupt number already described intended to reflect the cs
> function but did incorrectly describe the core block. This was not

I can't find the interrupt mapping table for V3U, so this is the only
thing I can't check

> noticed until now as the driver do not make use of the interrupt for the
> cs block.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>

The rest looks good

> ---
>  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++------
>  1 file changed, 44 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index f1613bfd1632..95ff69339991 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -2588,13 +2588,20 @@ du_out_dsi1: endpoint {
>  		isp0: isp@fed00000 {
>  			compatible = "renesas,r8a779a0-isp",
>  				     "renesas,rcar-gen4-isp";
> -			reg = <0 0xfed00000 0 0x10000>;
> -			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 612>;
> +			reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
> +			reg-names = "cs", "core";

However, won't the presence of a "core" part trigger the probing of
the forthcoming RPP core support, which should not support V3U as far
I understood ?

> +			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "cs", "core";
> +			clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
> +			clock-names = "cs", "core";
>  			power-domains = <&sysc R8A779A0_PD_A3ISP01>;
> -			resets = <&cpg 612>;
> +			resets = <&cpg 612>, <&cpg 16>;
> +			reset-names = "cs", "core";
>  			status = "disabled";
>
> +			renesas,vspx = <&vspx0>;
> +
>  			ports {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> @@ -2672,13 +2679,20 @@ isp0vin07: endpoint {
>  		isp1: isp@fed20000 {
>  			compatible = "renesas,r8a779a0-isp",
>  				     "renesas,rcar-gen4-isp";
> -			reg = <0 0xfed20000 0 0x10000>;
> -			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 613>;
> +			reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>;
> +			reg-names = "cs", "core";
> +			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "cs", "core";
> +			clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>;
> +			clock-names = "cs", "core";
>  			power-domains = <&sysc R8A779A0_PD_A3ISP01>;
> -			resets = <&cpg 613>;
> +			resets = <&cpg 613>, <&cpg 17>;
> +			reset-names = "cs", "core";
>  			status = "disabled";
>
> +			renesas,vspx = <&vspx1>;
> +
>  			ports {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> @@ -2756,13 +2770,20 @@ isp1vin15: endpoint {
>  		isp2: isp@fed30000 {
>  			compatible = "renesas,r8a779a0-isp",
>  				     "renesas,rcar-gen4-isp";
> -			reg = <0 0xfed30000 0 0x10000>;
> -			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 614>;
> +			reg = <0 0xfed30000 0 0x10000>, <0 0xfef00000 0 0x100000>;
> +			reg-names = "cs", "core";
> +			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "cs", "core";
> +			clocks = <&cpg CPG_MOD 614>, <&cpg CPG_MOD 18>;
> +			clock-names = "cs", "core";
>  			power-domains = <&sysc R8A779A0_PD_A3ISP23>;
> -			resets = <&cpg 614>;
> +			resets = <&cpg 614>, <&cpg 18>;
> +			reset-names = "cs", "core";
>  			status = "disabled";
>
> +			renesas,vspx = <&vspx2>;
> +
>  			ports {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> @@ -2840,13 +2861,20 @@ isp2vin23: endpoint {
>  		isp3: isp@fed40000 {
>  			compatible = "renesas,r8a779a0-isp",
>  				     "renesas,rcar-gen4-isp";
> -			reg = <0 0xfed40000 0 0x10000>;
> -			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 615>;
> +			reg = <0 0xfed40000 0 0x10000>, <0 0xfe400000 0 0x100000>;
> +			reg-names = "cs", "core";
> +			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "cs", "core";
> +			clocks = <&cpg CPG_MOD 615>, <&cpg CPG_MOD 19>;
> +			clock-names = "cs", "core";
>  			power-domains = <&sysc R8A779A0_PD_A3ISP23>;
> -			resets = <&cpg 615>;
> +			resets = <&cpg 615>, <&cpg 19>;
> +			reset-names = "cs", "core";
>  			status = "disabled";
>
> +			renesas,vspx = <&vspx3>;
> +
>  			ports {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> --
> 2.48.1
>




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