Quoting Biju Das (2025-03-03 03:04:19) > The spi and spix2 clk share same bit for clock gating. Add support > for coupled clock with checking the monitor bit for both the clocks. Could you add an intermediate parent clk of both spi and spix2 that only handles the enable bit for clock gating? Then the enable count handling would be in the core clk code.
