On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs
for extracting TSSEL and then update the macros ICU_TSSR_TSSEL_PREP and
ICU_TSSR_TSSEL_MASK for supporting both SoCs.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v5->v6:
* Dropped Rb tag from Geert as it retain macros instead of dropping it.
* Retained the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK by
adding field_width parameter.
v4->v5:
* Used tssr_shift_factor in rzv2h_tint_set_type to optimize the
calculation.
* Dropped unnecessary parenthesis for calculating tssr.
* Added Rb tag from Geert.
v4:
* New patch
---
drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index ac71ce9810f8..351303839636 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,13 @@
#define ICU_TINT_LEVEL_HIGH 2
#define ICU_TINT_LEVEL_LOW 3
-#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8))
-#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n)
+#define ICU_TSSR_TSSEL_PREP(tssel, n, f_width) ((tssel) << ((n) * (f_width)))
+#define ICU_TSSR_TSSEL_MASK(n, _field_width) \
+({\
+ typeof(_field_width) (field_width) = (_field_width); \
+ ICU_TSSR_TSSEL_PREP((GENMASK(((field_width) - 2), 0)), (n), field_width); \
+})
+
#define ICU_TSSR_TIEN(n, _field_width) \
({\
typeof(_field_width) (field_width) = (_field_width); \
@@ -326,8 +331,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
guard(raw_spinlock)(&priv->lock);
tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
- tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
- tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
+ tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);
+ tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
--
2.43.0
