Hi Prabhakar, > -----Original Message----- > From: Prabhakar <prabhakar.csengg@xxxxxxxxx> > Sent: 28 July 2025 21:15 > Subject: [PATCH v7 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add support for PLLDSI and PLLDSI divider clocks. > > Introduce the `renesas-rzv2h-cpg-pll.h` header to centralize and share PLLDSI related data structures, > limits, and algorithms between the > RZ/V2H(P) CPG and DSI drivers. > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly different parameter limits > and omits the programmable divider present in CPG. To ensure precise frequency calculations, especially > for milliHz-level accuracy needed by the DSI driver, the shared algorithm allows both drivers to > compute PLL parameters consistently using the same logic and input clock. > > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
