From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The write to PFC_OEN register is controlled by the write protect register
(PWPR). Currently OEN register write in resume() is done without enabling
the write access in PWPR leading to incorrect operation.
Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}")
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v1->v2:
* Updated commit description.
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b182b3b8a542..2b5d16594bb7 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3165,6 +3165,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+ unsigned long flags;
+ u8 pwpr;
int ret;
if (!atomic_read(&pctrl->wakeup_path)) {
@@ -3174,7 +3176,15 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
}
writeb(cache->qspi, pctrl->base + QSPI);
+ spin_lock_irqsave(&pctrl->lock, flags);
+ if (pctrl->data->hwcfg->oen_pwpr_lock) {
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ }
writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
+ if (pctrl->data->hwcfg->oen_pwpr_lock)
+ writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
for (u8 i = 0; i < 2; i++) {
if (regs->sd_ch)
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
--
2.43.0
