On Sun, 29 Jun 2025 at 22:39, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > > Wrong actual clock reported, if the SD clock division ratio is other > than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111). > > On high speed mode, cat /sys/kernel/debug/mmc1/ios > Without the patch: > clock: 50000000 Hz > actual clock: 200000000 Hz > > After the fix: > clock: 50000000 Hz > actual clock: 50000000 Hz > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Applied for next, thanks! Kind regards Uffe > --- > Note: > For HS400, the division ratio is 0. I don't have a board with HS400 mode > to verify the fix. > > I believe for HS400 Mode, > SDnH = 800MHz > Divider 2 = 400MHz > Division ratio 0 = 400 / 2 = 200MHz > > and for HS200/SDR-104 > SDnH = 800 MHz > Divider 4 = 200 MHz > Division ratio 1:1 = 200MHz > > Please correct me, if it is wrong. > --- > drivers/mmc/host/renesas_sdhi_core.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c > index fb8ca03f661d..a41291a28e9b 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -222,7 +222,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, > clk &= ~0xff; > } > > - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); > + clock = clk & CLK_CTL_DIV_MASK; > + if (clock != 0xff) > + host->mmc->actual_clock /= (1 << (ffs(clock) + 1)); > + > + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); > if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) > usleep_range(10000, 11000); > > -- > 2.43.0 >
