On Wed, 30 Jul 2025 at 18:46, Biju <biju.das.au@xxxxxxxxx> wrote:
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.
>
> v2->v3:
> * Added header file linux/io.h
> * Replaced io{read,write}64_rep->{read,write}sq to fix the build error
> reported by the bot.
> RFT->v2:
> * Collected tags
> * Fixed the build error reported by the bot.
>
> Biju Das (2):
> mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
> mmc: renesas_sdhi: Enable 64-bit polling mode
>
> drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +-
> drivers/mmc/host/tmio_mmc.h | 15 +++++++++
> drivers/mmc/host/tmio_mmc_core.c | 33 +++++++++++++++++++
> include/linux/platform_data/tmio.h | 3 ++
> 4 files changed, 53 insertions(+), 1 deletion(-)
>
The series applied for next, thanks!
Kind regards
Uffe
