From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC
DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index eeccd1345f71..0e6867ad112a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -552,6 +552,190 @@ channel5 {
};
};
+ gpt0: pwm@13010000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13010000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_CORE R9A09G047_GPT_0_CLKS_GPT>, <&cpg CPG_MOD 0x31>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x59>, <&cpg 0x5a>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@13020000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13020000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 610 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 618 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 626 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 658 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 627 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 659 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 628 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 636 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 652 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 660 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 621 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 629 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 637 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 661 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 614 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 622 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 630 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 646 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 662 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 631 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 647 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 663 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 632 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 656 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 617 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 625 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 633 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 665 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_CORE R9A09G047_GPT_1_CLKS_GPT>, <&cpg CPG_MOD 0x32>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x5b>, <&cpg 0x5c>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
--
2.43.0
