On Wed, 20 Aug 2025 at 12:30, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add clock and reset entries for the Renesas RZ/G3E GPT{0,1} IPs.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
> * Dropped the series as according to the clock system diagram and clock
> list sheets, gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt are really the
> same clocks.
> * Dropped R9A09G047_GPT_1_CLKS_GPT macro
> * Replaced DEF_MOD_PARENT->DEF_MOD for module clks.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
