Hi Geert, Thank you for the review. On Wed, Sep 3, 2025 at 10:09 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Tue, 2 Sept 2025 at 02:13, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Document the Ethernet MAC (GMAC) IP present on the Renesas RZ/T2H > > (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The GMAC IP on RZ/N2H is > > identical to that found on the RZ/T2H SoC. > > > > While the RZ/V2H(P), RZ/T2H, and RZ/N2H SoCs all integrate the Synopsys > > DesignWare MAC (version 5.20), the hardware is synthesized with different > > options compared to the RZ/V2H(P): > > - RZ/T2H requires only 3 clocks instead of 7 > > - RZ/T2H supports 8 RX/TX queue pairs instead of 4 > > - RZ/T2H needs 2 reset controls with reset-names property, vs. a single > > unnamed reset > > - RZ/T2H has the split header feature enabled, while it is disabled on > > RZ/V2H(P) > > > > To accommodate these differences, introduce a new generic compatible > > string `renesas,rzt2h-gbeth`, used as a fallback for both RZ/T2H and > > RZ/N2H SoCs. > > Until now, we didn't have any family-specific "renesas,rzt2h-*" > compatible values. Instead, we always used " renesas,r9a09g077-<foo>" > as a fallback for "renesas,r9a09g087-<foo>". > Is there any good reason to start deviating from this? > Right, I missed that! I 'll switch back to the previous approach. Cheers, Prabhakar
