Hi Geert,
> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 05 September 2025 10:40
> Subject: Re: [PATCH v2 1/2] pinctrl: renesas: rzg2l: Fix OEN resume
>
> Hi Biju,
>
> On Sun, 17 Aug 2025 at 16:30, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > The write to PFC_OEN register is controlled by the write protect
> > register (PWPR). Currently OEN register write in resume() is done
> > without enabling the write access in PWPR leading to incorrect operation.
> >
> > Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling
> > across RZ/{G2L,V2H,V2N}")
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> i.e. will queue in renesas-pinctrl for v6.18.
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>
> > @@ -3174,7 +3176,15 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
> > }
> >
> > writeb(cache->qspi, pctrl->base + QSPI);
> > + spin_lock_irqsave(&pctrl->lock, flags);
> > + if (pctrl->data->hwcfg->oen_pwpr_lock) {
> > + pwpr = readb(pctrl->base + regs->pwpr);
> > + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
> > + }
> > writeb(cache->oen, pctrl->base +
> > pctrl->data->hwcfg->regs.oen);
> > + if (pctrl->data->hwcfg->oen_pwpr_lock)
> > + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
> > + spin_unlock_irqrestore(&pctrl->lock, flags);
> > for (u8 i = 0; i < 2; i++) {
> > if (regs->sd_ch)
> > writeb(cache->sd_ch[i], pctrl->base +
> > SD_CH(regs->sd_ch, i));
>
> Would you mind if I moved the spin_*lock* calls inside the if-statements while applying?
It is ok for me.
Thanks,
Biju
