Add GPIO controllers (Synosys DesignWare IPs) available in the
r9a06g032 (RZ/N1D) SoC.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@xxxxxxxxxxx>
---
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 121 +++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 13a60656b044..da977cdd8487 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -499,6 +499,127 @@ gic: interrupt-controller@44101000 {
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ /*
+ * The GPIO mapping to the corresponding pins is not obvious.
+ * See the hardware documentation for details.
+ */
+ gpio0: gpio@5000b000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000b000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
+ clock-names = "bus";
+ status = "disabled";
+
+ /* GPIO0a[0] connected to pin GPIO0 */
+ /* GPIO0a[1..2] connected to pins GPIO3..4 */
+ /* GPIO0a[3..4] connected to pins GPIO9..10 */
+ /* GPIO0a[5] connected to pin GPIO12 */
+ /* GPIO0a[6..7] connected to pins GPIO15..16 */
+ /* GPIO0a[8..9] connected to pins GPIO21..22 */
+ /* GPIO0a[10] connected to pin GPIO24 */
+ /* GPIO0a[11..12] connected to pins GPIO27..28 */
+ /* GPIO0a[13..14] connected to pins GPIO33..34 */
+ /* GPIO0a[15] connected to pin GPIO36 */
+ /* GPIO0a[16..17] connected to pins GPIO39..40 */
+ /* GPIO0a[18..19] connected to pins GPIO45..46 */
+ /* GPIO0a[20] connected to pin GPIO48 */
+ /* GPIO0a[21..22] connected to pins GPIO51..52 */
+ /* GPIO0a[23..24] connected to pins GPIO57..58 */
+ /* GPIO0a[25..31] connected to pins GPIO62..68 */
+ gpio0a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+
+ /* GPIO0b[0..1] connected to pins GPIO1..2 */
+ /* GPIO0b[2..5] connected to pins GPIO5..8 */
+ /* GPIO0b[6] connected to pin GPIO11 */
+ /* GPIO0b[7..8] connected to pins GPIO13..14 */
+ /* GPIO0b[9..12] connected to pins GPIO17..20 */
+ /* GPIO0b[13] connected to pin GPIO23 */
+ /* GPIO0b[14..15] connected to pins GPIO25..26 */
+ /* GPIO0b[16..19] connected to pins GPIO29..32 */
+ /* GPIO0b[20] connected to pin GPIO35 */
+ /* GPIO0b[21..22] connected to pins GPIO37..38 */
+ /* GPIO0b[23..26] connected to pins GPIO41..44 */
+ /* GPIO0b[27] connected to pin GPIO47 */
+ /* GPIO0b[28..29] connected to pins GPIO49..50 */
+ /* GPIO0b[30..31] connected to pins GPIO53..54 */
+ gpio0b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <1>;
+ };
+ };
+
+ gpio1: gpio@5000c000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000c000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
+ clock-names = "bus";
+ status = "disabled";
+
+ /* GPIO1a[0..4] connected to pins GPIO69..73 */
+ /* GPIO1a[5..31] connected to pins GPIO95..121 */
+ gpio1a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+
+ /* GPIO1b[0..1] connected to pins GPIO55..56 */
+ /* GPIO1b[2..4] connected to pins GPIO59..61 */
+ /* GPIO1b[5..25] connected to pins GPIO74..94 */
+ /* GPIO1b[26..31] connected to pins GPIO150..155 */
+ gpio1b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <1>;
+ };
+ };
+
+ gpio2: gpio@5000d000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000d000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
+ clock-names = "bus";
+ status = "disabled";
+
+ /* GPIO2a[0..27] connected to pins GPIO122..149 */
+ /* GPIO2a[28..31] connected to pins GPIO156..159 */
+ gpio2a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+
+ /* GPIO2b[0..9] connected to pins GPIO160..169 */
+ gpio2b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <10>;
+ reg = <1>;
+ };
+ };
+
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
--
2.51.0
