In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO
Interrupt Multiplexer.
Add the multiplexer node and connect GPIO interrupt lines to the
multiplexer.
The interrupt-map available in the multiplexer node has to be updated in
dts files depending on the GPIO usage. Indeed, the usage of an interrupt
for a GPIO is board dependent.
Up to 8 GPIOs can be used as an interrupt line (one per multiplexer
output interrupt).
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@xxxxxxxxxxx>
---
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 49 ++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index da977cdd8487..3cd7ac38eb7a 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -534,6 +534,14 @@ gpio0a: gpio-port@0 {
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = < 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31 >;
+ #interrupt-cells = <2>;
};
/* GPIO0b[0..1] connected to pins GPIO1..2 */
@@ -576,6 +584,14 @@ gpio1a: gpio-port@0 {
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = < 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63 >;
+ #interrupt-cells = <2>;
};
/* GPIO1b[0..1] connected to pins GPIO55..56 */
@@ -608,6 +624,14 @@ gpio2a: gpio-port@0 {
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = < 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95 >;
+ #interrupt-cells = <2>;
};
/* GPIO2b[0..9] connected to pins GPIO160..169 */
@@ -620,6 +644,31 @@ gpio2b: gpio-port@1 {
};
};
+ gpioirqmux: interrupt-controller@51000480 {
+ compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+ reg = <0x51000480 0x20>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-map-mask = <0x7f>;
+
+ /*
+ * interrupt-map has to be updated according to GPIO
+ * usage. The order has to be kept. Only the src irq
+ * (0 field) has to be updated with the needed GPIO
+ * interrupt number.
+ */
+ interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
--
2.51.0
