Hi Geert, Thank you for the review. On Thu, Aug 14, 2025 at 4:23 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Tue, 12 Aug 2025 at 19:17, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Add asynchronous core clocks and module clocks for SCI channels 1 > > through 5 on the RZ/T2H SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a09g077-cpg.c > > +++ b/drivers/clk/renesas/r9a09g077-cpg.c > > @@ -48,6 +48,11 @@ > > #define DIVCA55S CONF_PACK(SCKCR2, 12, 1) > > > > #define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2) > > +#define DIVSCI1ASYNC CONF_PACK(SCKCR3, 8, 2) > > +#define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2) > > +#define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2) > > +#define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2) > > +#define DIVSCI5ASYNC CONF_PACK(SCKCR2, 18, 2) > > Please move the last one to the previous block, next to the other > SCKCR2 definitions. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > i.e. will queue in renesas-clk for v6.18, with the above fixed. > Thanks for taking care of it. Cheers, Prabhakar
